Power semiconductor devices are widely used to carry large currents and support high voltages. A wide variety of power semiconductor devices are known in the art including, for example, power Metal Oxide Semiconductor Field Effect Transistors (“MOSFET”), Insulated Gate Bipolar Transistors (“IGBT”), Schottky diodes, Junction Barrier Schottky (“JBS”) diodes, merged p-n Schottky (“MPS”) diodes, Gate Turn-Off Transistors (“GTO”), MOS-controlled thyristors and various other devices. Modern power semiconductor devices are generally fabricated from monocrystalline silicon semiconductor material, or, more recently, from silicon carbide (“SiC”) or gallium nitride (“GaN”) based semiconductors.
Power semiconductor devices can have a lateral structure or a vertical structure. In a lateral structure, the terminals of the device (e.g., the drain, gate and source terminals for a power MOSFET device) are on the same major surface (i.e., top or bottom) of a semiconductor layer structure. In contrast, in a vertical structure, terminals are provided on both major surfaces of the semiconductor layer structure (e.g., in a vertical MOSFET, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. Herein, the term “semiconductor layer structure” refers to a structure that includes at least two semiconductor layers in a stacked relationship or to at least a single semiconductor layer having regions that are doped with different types of dopants.
A conventional silicon carbide power device typically has a silicon carbide substrate such as a silicon carbide wafer having a first conductivity type (e.g., an n-type substrate) on which an epitaxial layer having the first conductivity type (e.g., n-type) is formed. This epitaxial layer (which may comprise one or more separate layers) functions as a drift region of the power semiconductor device. The device typically includes an “active region” which includes one or more power semiconductor devices that have a p-n junction and/or a Schottky junction. The active region may be formed on and/or in the drift region. The active region acts as a main junction for blocking voltage in the reverse bias direction and providing current flow in the forward bias direction. The device may also have an edge termination region that is adjacent the active region. One or more power semiconductor devices may be formed on the substrate, and each power semiconductor device will typically have its own edge termination. After the substrate is fully formed and processed, the substrate may be diced to separate the individual edge-terminated power semiconductor devices if multiple devices are formed on the same substrate. In many cases, the power semiconductor devices on the substrate may have a unit cell structure in which the active region of each power semiconductor device includes a large number of individual devices that are disposed in parallel to each other and that together function as a single power semiconductor device.
Power semiconductor devices are designed to block (in the forward or reverse blocking state) or pass (in the forward operating state) large voltages and/or currents. For example, in the blocking state, a power semiconductor device may be designed to sustain tens, hundreds or thousands of volts of electric potential, or even higher voltages. However, as the voltage approaches or passes the voltage level that the device is designed to block, non-trivial levels of current may begin to flow through the power semiconductor device. Such current, which is typically referred to as “leakage current,” may be highly undesirable. Leakage current may begin to flow if the voltage is increased beyond the design voltage blocking capability of the device, which may be a function of, among other things, the doping and thickness of the drift layer. However, current leakage can occur for other reasons, such as failure of the edge termination and/or the primary junction of the device. If the voltage on the device is increased past the breakdown voltage to a critical level which is referred to as the theoretical avalanche breakdown point, the increasing electric field may result in runaway generation of charge carriers within the semiconductor device, leading to a condition known as avalanche breakdown. When avalanche breakdown occurs, the reverse current increases sharply and typically becomes uncontrollable. When uncontrolled, such failures are generally catastrophic, and may damage or destroy the power semiconductor device.
A power semiconductor device may also begin to break down and allow non-trivial amounts of leakage current to flow at a voltage that is lower than the design breakdown voltage of the device. In particular, leakage current may begin to flow at the edges of the active region, where high electric fields may be experienced due to electric field crowding effects. In order to reduce this electric field crowding (and the resulting increased leakage currents), edge termination structures may be provided that surround part or all of the active region of a power semiconductor device. These edge terminations may spread the electric field out over a greater area, thereby reducing the electric field crowding.
Conventionally, a tradeoff exists in vertical power semiconductor devices between the breakdown voltage of the device and the doping level of the drift region. In particular, to increase the breakdown voltage of the device, it was necessary to decrease the doping concentration of the drift region and to increase the thickness of the drift region. Since the drift region is the current path for the device in the forward “on” state, the decreased doping concentration in the drift region may result in a higher on-state resistance for the device, which may be undesirable in many applications.
Recently, superjunction-type drift regions have been introduced in which the drift region is divided into alternating, side-by-side heavily-doped n-type and p-type regions. In vertical semiconductor devices, these side-by-side n-type and p-type regions are often referred to as “pillars.” The thickness and doping of these pillars may be controlled so that the superjunction will act like a p-n junction with low resistance and a high breakdown voltage.
FIG. 1 is a schematic cross-sectional diagram of a conventional power semiconductor device in the form of a JBS diode 10 that has a superjunction-type drift region 30. As shown in FIG. 1, the JBS diode 10 includes a cathode contact 20, an ohmic contact layer 22, an n-type substrate 24, a drift region 30 a p-type blocking junction 40, a channel region 46, a Schottky contact 42 and an anode contact 44. The cathode contact 20 and the anode contact 44 may each comprise a highly conductive metal layer. The Schottky contact 42 may comprise a layer that forms a Schottky junction with the drift region 30 and may comprise, for example, an aluminum layer. The n-type substrate 24 may comprise a silicon carbide substrate that is heavily doped with n-type impurities such as nitrogen or phosphorous. The ohmic contact layer 22 may comprise a metal that forms an ohmic contact to n-type silicon carbide so as to form an ohmic contact to the silicon carbide substrate 24. The substrate 24 may comprise, for example, an n+ silicon carbide wafer. The p-type blocking junction 40 may be a p-type implanted region in an upper portion of the drift region 30 that is heavily implanted with p-type dopants. The channel region 46 is positioned adjacent the p-type blocking junction 40. The channel region 46 is a semiconductor structure that passes current in the on-state and blocks voltage in the blocking state. Current flows through the channel region 46 when the diode 10 is in its forward on-state.
The drift region 30 may comprise a silicon carbide semiconductor region that includes an n-type pillar 32 and a p-type pillar 34. The n-type pillar 32 and the p-type pillar 34 may each comprise epitaxially grown silicon carbide layers that are doped with n-type and p-type dopants, respectively, via ion implantation. The number of charges in the n-type pillar 32 may be approximately equal to the number of charges in the p-type pillar 34.